This invention relates to a method of fabrication of a metal-semiconductor field effect transistor and a structure for such a transistor; and it relates in particular to the method of forming the gate electrode for such transistors.
Fabrication of a metal semiconductor field effect transistor (MESFET, or more commonly, a FET) involves forming drain, source, and gate electrodes on the surface of a semiconductor wafer. Ohmic contacts are generally used for the drain and source electrodes whereas a Schottky barrier metal alloy or system is used for the gate electrode.
Presently, techniques are used in fabricating gate electrodes in an attempt to achieve short gate lengths, low electrical resistance along the width of the gate, and the option to pre-etch the semiconductor wafer before gate metallization is done.
A technique which is currently used in fabricating gate electrodes involves depositing a photoresist layer on a semiconductor wafer surface and then forming an opening in the photoresist layer, thereby exposing the underlying wafer surface. A metal layer is deposited by angle evaporation techniques over the wafer surface and is then removed in selected regions, leaving only the gate electrode. Here gate lengths which are shorter than the photoresist opening can be obtained and the semiconductor wafer can be etched in the gate area before metal deposition to create a gate trough region. However, excessively large gate trough regions are created, and contamination is introduced during processing in this region, resulting in degradation of device transconductance and gain. This technique is described in an article entitled "Sub-micrometer MESFETS Fabricated on Various GaAs Substrates" by C. Li, P. T. Chen, and P. H. Wang published in The Institute of Physics Conference, Ser. No. 45: Chapter 4, 1979. In the method described in the foregoing article, a dielectric layer used for passivation purposes is formed over the structure after gate electrode formation and the electrical resistance of the resulting gate electrode structure is undesirably high (i.e. greater than 12 ohm per 100 micrometer gate width). In fact, because the dielectric layer is formed over the structure after the gate electrode formed, protection of the sensitive gate area during subsequent processing is not done at all.
Another gate fabrication technique which offers low electrical resistance of the gate electrode involves depositing a first photoresist layer on top of a semiconductor material and then forming openings in the first photoresist layer, corresponding to the gate electrode. In one embodiment, when drain and source electrodes have been previously formed, additional openings in the first layer of the photoresist are formed that approximately overlay the drain and source electrodes. A first metal layer is deposited on top of this structure. A second photoresist layer is then deposited on top of the first metal layer; large openings are formed in the second photoresist layer which overlay the openings in the first layer of photoresist. The thickness of the gate electrode, and in one embodiment, the sections overlaying the drain and source electrodes, is then increased by plating gold into the openings in the second layer of photoresist. This technique is disclosed in a U.S. Pat. No. 4,213,840 by Masahiro Omori, James N. Wholey, and J. Ross Anderson, entitled "Low-Resistance, Fine-line Semiconductor Device And The Method For Its Manufacture" issued July 22, 1980. Using this technique it is difficult for one to achieve sub-micron lines with optical lithography methods. In fact, this technique does not solve the contamination problems introduced during subsequent processing but further introduces process controllability and repeatability problems.